Energy-efficient circuits and systems for computational imaging and vision on mobile devices

Thesis: Ph. D., Massachusetts Institute of Technology, Department of Electrical Engineering and Computer Science, 2018.Cataloged from PDF version of thesis.Includes bibliographical references (pages 125-127).Eighty five percent of images today are taken by cell phones. These images are not merely projections of light from the scene onto the camera sensor but result from a deep calculation. This calculation involves a number of computational imaging algorithms such as high dynamic range (HDR) imaging, panorama stitching, image deblurring and low-light imaging that compensate for camera limitations, and a number of deep learning based vision algorithms such as face recognition, object recognition and scene understanding that make inference on these images for a variety of emerging applications. However, because of their high computational complexity, mobile CPU or GPU based implementations of these algorithms do not achieve real-time performance. Moreover, offloading these algorithms to the cloud is not a viable solution because wirelessly transmitting large amounts of image data results in long latency and high energy consumption, making them unsuitable for mobile devices. This work solves these problems by designing energy-efficient hardware accelerators targeted at these applications. It presents the architecture of two complete computational imaging systems for energy-constrained mobile environments: (1) an energy-scalable accelerator for blind image deblurring, with an on-chip implementation and (2) a low-power processor for real-time motion magnification in videos, with an FPGA implementation. It also presents a 3D imaging platform and image processing workflow for 3D surface area assessment of dermatologic lesions. It demonstrates that such accelerator-based systems can enable energy-efficient integration of computational imaging and vision algorithms into mobile and wearable devices.by Priyanka Raina.Ph. D

Architectures for computational photography

Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Electrical Engineering and Computer Science, 2013.Cataloged from PDF version of thesis.Includes bibliographical references (p. 93-94).Computational photography refers to a wide range of image capture and processing techniques that extend the capabilities of digital photography and allow users to take photographs that could not have been taken by a traditional camera. Since its inception less than a decade ago, the field today encompasses a wide range of techniques including high dynamic range (HDR) imaging, low light enhancement, panorama stitching, image deblurring and light field photography. These techniques have so far been software based, which leads to high energy consumption and typically no support for real-time processing. This work focuses on hardware architectures for two algorithms - (a) bilateral filtering which is commonly used in computational photography applications such as HDR imaging, low light enhancement and glare reduction and (b) image deblurring. In the first part of this work, digital circuits for three components of a multi-application bilateral filtering processor are implemented - the grid interpolation block, the HDR image creation and contrast adjustment blocks, and the shadow correction block. An on-chip implementation of the complete processor, designed with other team members, performs HDR imaging, low light enhancement and glare reduction. The 40 nm CMOS test chip operates from 98 MHz at 0.9 V to 25 MHz at 0.9 V and processes 13 megapixels/s while consuming 17.8 mW at 98 MHz and 0.9 V, achieving significant energy reduction compared to previous CPU/GPU implementations. In the second part of this work, a complete system architecture for blind image deblurring is proposed. Digital circuits for the component modules are implemented using Bluespec SystemVerilog and verified to be bit accurate with a reference software implementation. Techniques to reduce power and area cost are investigated and synthesis results in 40nm CMOS technology are presentedby Priyanka Raina.S.M

Pap smear in antenatal women: a valuable opportunity for screening and awareness

Background: Pregnancy creates an important opportunity to screen the cervix for neoplastic and infectious diseases and to spread awareness. A pap smear is simple, cost effective and safe in pregnancy. In low resource countries, this may be the only opportunity when the woman visits a health centre.  It also helps identify and treat infections that could hamper the pregnancy outcome. Objective of the study is to determine the awareness of pap smear as a cervical cancer screening test in antenatal women; to determine the incidence of cervical neoplasia and premalignant lesions of the cervix in antenatal women.Methods: A cross-sectional study was carried out between November 2018 to April 2019. Inclusion criteria were pregnant women in the first trimester. Exclusion criteria were pregnancy greater than 12 weeks, symptoms of vaginal infection, history of sexual intercourse or vaginal medication or bleeding in the last 48 hours or a normal pap smear in the last 3 years. The reporting was done as per Bethesda 2014.Results: 308 women underwent a pap smear in their 1st trimester. 94% were satisfactory smears and 3(0.9%) an abnormal smear (2 LSIL and 1 ASCUS). 31.2% had inflammatory smears. Only 15 women were aware of pap smear as a test for cancer cervix screening and all these women were graduates and above. No women had ever had a pap smear test in the past. One fifth of women studied had 1 or more risk factor the commonest being early age at first intercourse.Conclusions: The antenatal period should be utilized as an opportunity to screen women for cancer cervix

A rare case of successful pregnancy outcome with giant paraovarian cyst: a case report and review of literature

A successful outcome of a pregnancy with huge paraovarian cyst in a 29 year old female who presented with 16 weeks of gestation with ultra-sonography suggestive of huge mesenteric cyst. Pregnancy was carried till 35 weeks of gestation. Exploratory laparotomy was done where a giant paraovariancyst of size 35cm x 20 cm x 15 cm, weighing 2kg was found. Baby was delivered by lower segment caesarean section and cystectomy was performed

Knowledge, Attitude, and Practice of Health Care Workers in Management of Bio-Medical Waste – A Cross-Sectional Study

Background: Management of Bio-Medical Waste involves a great concern. Therefore, awareness of Health-Care Workers (HCWs) becomes very important as improper management leads to injuries and the spread of infection to the staff, patients, and environment. The objective is to assess the Knowledge, Attitude, and Practice (KAP) among Health Care Professionals regarding Bio-Medical Waste Management (BMWM). Method: This cross-sectional survey was conducted among HCWs at GMC Jammu, India. Study participants were divided into III groups (Group I- 32 Doctors, group II- 48 Paramedical staff including nurses & laboratory technicians, and group III- 20 sanitary workers). Data was collected using a pre-designed questionnaire regarding BMWM and scored as good, average, and poor. Results: In our study, knowledge regarding symbols of BMWM and awareness regarding categories and segregation of BMW was good in I and II groups but averaged in group III. None in group III has attended CME regarding BMWM in the past. In contrast, this percentage was 61% in group II and 31% in group I. Regarding the capping and destroying of needles, 88% of Paramedics were doing it correctly. None of the class IV employees received the booster dose of HBV vaccination. Conclusion: Knowledge regarding BMWM was average in Group I and Group II, whereas Group III had the slightest knowledge. Attitude regarding the BMW was good in the case of groups I and II, Whereas Group III scored average. Practices were scored average in Group I, good in Group II, and poor in group III

Assessment of Oral Health Care Delivery System in Greater Noida Using Five A’s Model

BACKGROUND: Access to dental health services refers not only to utilization but also to the extent by which the utilization is judged as per the professional norms using five independent dimensions of accessibility, availability, accommodation, affordability and acceptability. AIM: The aim of the study is to assess the dental services utilization among population of Greater Noida using Five A’s model. MATERIALS AND METHOD: The study was conducted in Dental College in Greater Noida. This cross-sectional study was carried out on the 200 subjects using convenient sampling on the patients visiting dental OPD.A self-administered structured questionnaire in English and Hindi language was used. Data was entered in the Microsoft excel sheet and analysed using SPSS (version 20.0).RESULTS: Mean level of access to dental services in the study population was 60.3.Corresponding figures for affordability, availability, accessibility, accommodation and acceptability were 55.2 ± 12.1,57.1± 12.8,60.75 ± 14.7,61.75 ± 8.7,58.65± 11.4 respectively.CONCLUSION: According to the results of our study , the level of access to dental care services is not very good with family income, location and level of education being the determinants of this access

PEak: A Single Source of Truth for Hardware Design and Verification

Domain-specific languages for hardware can significantly enhance designer productivity, but sometimes at the cost of ease of verification. On the other hand, ISA specification languages are too static to be used during early stage design space exploration. We present PEak, an open-source hardware design and specification language, which aims to improve both design productivity and verification capability. PEak does this by providing a single source of truth for functional models, formal specifications, and RTL. PEak has been used in several academic projects, and PEak-generated RTL has been included in three fabricated hardware accelerators. In these projects, the formal capabilities of PEak were crucial for enabling both novel design space exploration techniques and automated compiler synthesis

A 0.6V, 8mW 3D Vision Processor for a Navigation Device for the Visually Impaired

This paper presents an energy-efficient computer vision processor for a navigation device for the visually impaired. Utilizing a shared parallel datapath, out-of-order processing and co-optimization with hardware-oriented algorithms, the processor consumes 8mW at 0.6V while processing 30 fps input data stream in real time. The test chip fabricated in 40nm is demonstrated as a core part of a navigation device based on a ToF camera, which successfully detects safe areas and obstacles.Texas Instruments Incorporate

Interstellar: Using Halide's Scheduling Language to Analyze DNN Accelerators

We show that DNN accelerator micro-architectures and their program mappings represent specific choices of loop order and hardware parallelism for computing the seven nested loops of DNNs, which enables us to create a formal taxonomy of all existing dense DNN accelerators. Surprisingly, the loop transformations needed to create these hardware variants can be precisely and concisely represented by Halide's scheduling language. By modifying the Halide compiler to generate hardware, we create a system that can fairly compare these prior accelerators. As long as proper loop blocking schemes are used, and the hardware can support mapping replicated loops, many different hardware dataflows yield similar energy efficiency with good performance. This is because the loop blocking can ensure that most data references stay on-chip with good locality and the processing units have high resource utilization. How resources are allocated, especially in the memory system, has a large impact on energy and performance. By optimizing hardware resource allocation while keeping throughput constant, we achieve up to 4.2X energy improvement for Convolutional Neural Networks (CNNs), 1.6X and 1.8X improvement for Long Short-Term Memories (LSTMs) and multi-layer perceptrons (MLPs), respectively.Comment: Published as a conference paper at ASPLOS 202